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IDTTM InterpriseTM Integrated Communications Processor
79RC32332--Rev. Y
Features
RC32300 32-bit Microprocessor - Up to 150 MHz operation - Enhanced MIPS-II Instruction Set Architecture (ISA) - Cache prefetch instruction - Conditional move instruction - DSP instructions - Supports big or little endian operation - MMU with 32 page TLB - 8KB Instruction Cache, 2-way set associative - 2KB Data Cache, 2-way set associative - Cache locking per line - Programmable on a page basis to implement a write-through no write allocate, write-through write allocate, or write-back algorithms for cache management - Compatible with a wide variety of operating systems Local Bus Interface - Up to 75 MHz operation - 23-bit address bus - 32-bit data bus - Direct control of local memory and peripherals - Programmable system watch-dog timers - Big or little endian support Interrupt Controller simplifies exception management Four general purpose 32-bit timer/counters
Programmable I/O (PIO) - Input/Output/Interrupt source - Individually programmable SDRAM Controller (32-bit memory only) - 4 banks, non-interleaved - Up to 512MB total SDRAM memory supported - Implements full, direct control of discrete, SODIMM, or DIMM memories - Supports 16Mb through 512Mb SDRAM device depths - Automatic refresh generation Serial Peripheral Interface (SPI) master mode interface UART Interface - 16550 compatible UART - Baud rate support up to 1.5 Mb/s Memory & Peripheral Controller - 6 banks, up to 8MB per bank - Supports 8-,16-, and 32-bit interfaces - Supports Flash ROM, SRAM, dual-port memory, and peripheral devices - Supports external wait-state generation - 8-bit boot PROM support - Flexible I/O timing protocols
Block Diagram
EJTAG In-Circuit Emulator Interface RISCore 32300 Enhanced MIPS-II ISA Integer CPU RC5000 Compatible CP0 32-page TLB
Interrupt Control Programmable I/O 32-bit Timers SPI Control DMA Control Local Memory/IO Control
UART
IPBus Bridge
2KB 2-set, Lockable Data Cache 8KB 2-set Lockable Instr. Cache
Figure 1 RC32332 Block Diagram
IDT Peripheral Bus
SDRAM Control
PCI Bridge
Note: This data sheet does not apply to revision Z silicon. Contact your IDT sales representative for information on revision Z.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2002 Integrated Device Technology, Inc.
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DSC 5701
IDT 79RC32332--Rev. Y
4 DMA Channels - 4 general purpose DMA, each with endianess swappers and byte lane data alignment - Supports scatter/gather, chaining via linked lists of records - Supports memory-to-memory, memory-to-I/O, memory-toPCI, PCI-to-PCI, and I/O-to-I/O transfers - Supports unaligned transfers - Supports burst transfers - Programmable DMA bus transactions burst size (up to 16 bytes) PCI Bus Interface - 32-bit PCI, up to 50 MHz - Revision 2.2 compatible - Target or master - Host or satellite - Two slot PCI arbiter - Serial EEPROM support, for loading configuration registers Off-the-shelf development tools JTAG Interface (IEEE Std. 1149.1 compatible) 208 QFP Package 3.3V operation with 5V compatible I/O EJTAG in-circuit emulator interface
CPU Execution Core
The RC32332 integrates the RISCore 32300, the same CPU core found in the award-winning RC32364 microprocessor. The RISCore 32300 implements the Enhanced MIPS-II ISA. Thus, it is upwardly compatible with applications written for a wide variety of MIPS architecture processors, and it is kernel compatible with the modern operating systems that support IDT's 64-bit RISController product family. The RISCore 32300 was explicitly defined and designed for integrated processor products such as the RC32332. Key attributes of the execution core found within this product include: High-speed, 5-stage scalar pipeline executes to 150MHz. This high performance enables the RC32332 to perform a variety of performance intensive tasks, such as routing, DSP algorithms, etc. 32-bit architecture with enhancements of key capabilities. Thus, the RC32332 can execute existing 32-bit programs, while enabling designers to take advantage of recent advances in CPU architecture. Count leading-zeroes/ones. These instructions are common to a wide variety of tasks, including modem emulation, voice over IP compression and decompression, etc. Cache PREFetch instruction support, including a specialized form intended to help memory coherency. System programmers can allocate and stage the use of memory bandwidth to achieve maximum performance. 8KB of 2-way set associative instruction cache
Device Overview
The IDT RC32332 device is an integrated processor based on the RC32300 CPU core. This product incorporates a high-performance, lowcost 32-bit CPU core with functionality common to a large number of embedded applications. The RC32332 integrates these functions to enable the use of low-cost PC commodity market memory and I/O devices, allowing the aggressive price/performance characteristics of the CPU to be realized quickly into low-cost systems.
Serial Channel Programmable I/O Serial EEPROM
RC32332 Integrated Core Controller
SDRAM
Local Memory I/O Bus
FLASH
Local I/O
32-bit, 33MHz PCI
Figure 2 RC32332 Based System Diagram
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2KB of 2-way set associative data cache, capable of write-back and write-through operation. Cache locking per line to speed real-time systems and critical system functions On-chip TLB to enable multi-tasking in modern operating systems EJTAG interface to enable sophisticated low-cost in-circuit emulation.
PCI Bus Bridge
In order to leverage the wide availability of low-cost peripherals for the PC market as well as to simplify the design of add-in functions, the RC32332 integrates a full 32-bit PCI bus bridge. Key attributes of this bridge include: 50 MHz operation PCI revision 2.2 compliant Programmable address mappings between CPU/Local memory and PCI memory and I/O On-chip PCI arbiter Extensive buffering allows PCI to operate concurrently with local memory transfers Selectable byte-ordering swapper 5V tolerant I/O.
Synchronous-DRAM Interface
The RC32332 integrates a SDRAM controller which provides direct control of system SyncDRAM running at speeds to 75MHz. Key capabilities of the SDRAM controller include: Direct control of 4 banks of SDRAM (up to 2 64-bit wide DIMMs) On-chip page comparators optimize access latency. Speeds to 75MHz Programmable address map. Supports 16, 64, 128, 256, or 512Mb SDRAM devices Automatic refresh generation driven by on-chip timer Support for discrete devices, SODIMM, or DIMM modules. Thus, systems can take advantage of the full range of commodity memory that is available, enabling system optimization for cost, realestate, or other attributes.
On-Chip DMA Controller
To minimize CPU exception handling and maximize the efficiency of system bandwidth, the RC32332 integrates a very sophisticated 4channel DMA controller on chip. The RC32332 DMA controller is capable of: Chaining and scatter/gather support through the use of a flexible, linked list of DMA transaction descriptors Capable of memory<->memory, memory<->I/O, and PCI<->memory DMA Unaligned transfer support Byte, halfword, word, quadword DMA support.
Local Memory and I/O Controller
The local memory and I/O controller implements direct control of external memory devices, including the boot ROM as well as other memory areas, and also implements direct control of external peripherals. The local memory controller is highly flexible, allowing a wide range of devices to be directly controlled by the RC32332 processor. For example, a system can be built using an 8-bit boot ROM, 16-bit FLASH cards (possibly on PCMCIA), a 32-bit SRAM or dual-port memory, and a variety of low-cost peripherals. Key capabilities include: Direct control of EPROM, FLASH, RAM, and dual-port memories 6 chip-select outputs, supporting up to 8MB per memory space Supports mixture of 8-, 16-, and 32-bit wide memory regions Flexible timing protocols allow direct control of a wide variety of devices Programmable address map for 2 chip selects Automatic wait state generation.
On-Chip Peripherals
The RC32332 also integrates peripherals that are common to a wide variety of embedded systems. Single 16550 compatible UART. SPI master mode interface for direct interface to EEPROM, A/D, etc. Interrupt Controller to speed interrupt decode and management Four 32-bit on-chip Timer/Counters Programmable I/O module
Debug Support
To facilitate rapid time to market, the RC32332 provides extensive support for system debug. First and foremost, this product integrates an EJTAG in-circuit emulation module, allowing a low-cost emulator to interoperate with programs executing on the controller. By using an augmented JTAG interface, the RC32332 is able to reuse the same low-cost emulators developed around the RC32364 CPU.
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Secondly, the RC32332 implements additional reporting signals intended to simplify the task of system debugging when using a logic analyzer. This product allows the logic analyzer to differentiate transactions initiated by DMA from those initiated by the CPU and further allows CPU transactions to be sorted into instruction fetches vs. data fetches. Finally, the RC32332 implements a full boundary scan capability, allowing board manufacturing diagnostics and debug.
November 1, 2001: Added Input Voltage Undershoot parameter and 2 footnotes to Table 10. Changed to DH package. May 2, 2002: Changed from PCI 2.1 to 2.2 compliant. Added 512 MB SDRAM support. Changed upper ambient temperature for commercial uses back from +85 C to +70 C (changed erroneously from 70 to 85 on March 13, 2001). Added Reset State Status column to Table 1. Revised description of jtag_trst_n in Table 1 and changed this pin to a pull-down instead of a pull-up. July 3, 2002: This data sheet now describes revision Y silicon and is no longer applicable to revision Z. July 12, 2002: Added 150MHz speed grade. In Table 6: DMA section, changed Thld9 Min values from 2 to 1; in PIO section, changed Thld9 Min values from 2 to 1. Changed revision Y data sheet from Preliminary to Final. September 18, 2002: Added cpu_coldreset_n rise time to Table 5, Clock Parameters. Added mem_addr[16] and sdram_addr[16] to Tables 1 and 12. Changed Logic Diagram to include sdram_addr[16]. December 18, 2002: In the Reset section of Table 6, AC Timing Characteristics, setup and hold time categories for cpu_coldreset_n have been deleted.
Packaging
The RC32332 is packaged using a 208 Quad Flat Pack (QFP) package.
Thermal Considerations
The RC32332 consumes less than 2.0 W peak power. The device is guaranteed in an ambient temperature range of 0 to +70 C for commercial temperature devices; -40 to +85 C for industrial temperature devices.
Revision History
November 15, 2000: Initial publication. December 12, 2000: Changed Max values for cpu_masterclock period in Table 5 and added footnote. In Table 1, added 2nd alternate function for spi_mosi, spi_miso, spi_sck. In Table 11, added "2" in Alt column for pins 186, 187, 188. In RC32332 Alternate Signal Functions table, added pin names in Alt #2 column for pins 186, 187, 188. January 4, 2001: In Table 6 under Interrupt Handling, changed Tdoh9 to Thld13 and moved the values for Tsu9 from the Max to the Min column. February 23, 2001: In Table 1, changed alternate function for uart_tx[0] from PIO[3] to PIO[1]. In Table 11, changed the number of alternate pins for Pin 156 from 1 to 2. In Table 12, added PIO[7] to Alt #2 column for Pin 156 and changed PIO[3] to PIO[1] for Pin 207. March 13, 2001: Changed upper ambient temperature for industrial and commercial uses from +70 C to +85 C. June 7, 2001: In the Clock Parameters table, added footnote 3 to output_clk category and added NA to Min and Max columns. In Figure 3 (Reset Specification), enhanced signal line for cpu_masterclk. In Local System Interface section of AC Timing Characteristics table, changed values in Min column for last category of signals (Tdoh3) from 1.5 to 2.5 for both speeds. In SDRAM Controller section of same table, changed values in Min column for last category of signals (9 signals) from 1 to 2.5 for both speeds. September 14, 2001: In the Reset category of Table 6: switched mem_addr[19:17] from Tsu22 and Thld22 to Tsu10 and Thld10; switched mem_addr[22:20] from Tsu10 and Thld10 to Tsu22 and Thld22; moved ejtag_pcst[2:0] from Reset to Debug Interface category under Tsu20 and Thld20.
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Pin Description Table
The following table lists the pins provided on the RC32332. Note that those pin names followed by "_n" are active-low signals. All external pull-ups and pull-downs require 10 k resistor.
Name
Type
Drive Reset Strength State Status Capability
Description
Local System Interface mem_data[31:0] mem_addr[22:2] I/O I/O Z [22:10] Z [9:2] L High Local system data bus Primary data bus for memory. I/O and SDRAM.
[22:17] Low Memory Address Bus These signals provide the Memory or DRAM address, during a Memory or DRAM bus transaction. During [16:2] High each word data, the address increments either in linear or sub-block ordering, depending on the transaction type. The table below indicates how the memory write enable signals are used to address discreet memory port width types. Port Width 32-bit 16-bit 8-bit Pin Signals mem_we_n[3] mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[2] mem_we_n[2] mem_we_n[1] mem_we_n[1] Not Used (Driven Low) mem_addr[0] mem_we_n[0] mem_we_n[0] mem_we_n[0] Byte Low Write Enable Byte Write Enable
DMA (32-bit) mem_we_n[3]
Byte High Write Enable mem_addr[1] Not Used (Driven High) mem_addr[1]
mem_addr[22] Alternate function: reset_boot_mode[1]. mem_addr[21] Alternate function: reset_boot_mode[0]. mem_addr[20] Alternate function: reset_pci_host_mode. mem_addr[19] Alternate function: modebit [9]. mem_addr[18] Alternate function: modebit [8]. mem_addr[17] Alternate function: modebit [7]. mem_addr[16] Alternate function: sdram_addr[16]. mem_addr[15] Alternate function: sdram_addr[15]. mem_addr[14] Alternate function: sdram_addr[14]. mem_addr[13] Alternate function: sdram_addr[13]. mem_addr[11] Alternate function: sdram_addr[11]. mem_addr[10] Alternate function: sdram_addr[10]. mem_addr[9] Alternate function: sdram_addr[9]. mem_addr[8] Alternate function: sdram_addr[8]. mem_addr[7] Alternate function: sdram_addr[7]. mem_addr[6] Alternate function: sdram_addr[6]. mem_addr[5] Alternate function: sdram_addr[5]. mem_addr[4] Alternate function: sdram_addr[4]. mem_addr[3] Alternate function: sdram_addr[3]. mem_addr[2] Alternate function: sdram_addr[2]. mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] Output Output Output H H H Low High High Memory Chip Select Negated Recommend an external pull-up. Signals that a Memory Bank is actively selected. Memory Output Enable Negated Recommend an external pull-up. Signals that a Memory Bank can output its data lines onto the cpu_ad bus. Memory Write Enable Negated Bus Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing. Table 1 Pin Descriptions (Part 1 of 6)
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Name
Type
Description
mem_wait_n
Input
--
Memory Wait Negated Requires an external pull-up. SRAM/IOI/IOM modes: Allows external wait-states to be injected during the last cycle before data is sampled. DPM (dual-port) mode: Allows dual-port busy signal to restart memory transaction. Alternate function: sdram_wait_n. Memory FCT245 Output Enable Negated Controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to a memory or I/O bank. Memory FCT245 Direction Xmit/Rcv Negated Recommend an external pull-up. Alternate function: cpu_dt_r_n. See CPU Core Specific Signals below. Output Clock Optional clock output. PCI Multiplexed Address/Data Bus Address driven by Bus Master during initial frame_n assertion, and then the Data is driven by the Bus Master during writes; or the Data is driven by the Bus Slave during reads. PCI Multiplexed Command/Byte Enable Bus Command (not negated) Bus driven by the Bus Master during the initial frame_n assertion. Byte Enable Negated Bus driven by the Bus Master during the data phase(s). PCI Parity Even parity of the pci_ad[31:0] bus. Driven by Bus Master during Address and Write Data phases. Driven by the Bus Slave during the Read Data phase. PCI Frame Negated Driven by the Bus Master. Assertion indicates the beginning of a bus transaction. De-assertion indicates the last datum. PCI Target Ready Negated Driven by the Bus Slave to indicate the current datum can complete. PCI Initiator Ready Negated Driven by the Bus Master to indicate that the current datum can complete. PCI Stop Negated Driven by the Bus Slave to terminate the current bus transaction. PCI Initialization Device Select Uses pci_req_n[2] pin. See the PCI subsection. PCI Parity Error Negated Driven by the receiving Bus Agent 2 clocks after the data is received, if a parity error occurs. System Error Requires an external pull-up. Driven by any agent to indicate an address parity error, data parity during a Special Cycle command, or any other system error. PCI Clock Clock for PCI Bus transactions. Uses the rising edge for all timing references. PCI Reset Negated Host mode: Resets all PCI related logic. Satellite mode: with boot from PCI mode: Resets all PCI related logic and also warm resets the 32332. PCI Device Select Negated Driven by the target to indicate that the target has decoded the present address as a target address. Table 1 Pin Descriptions (Part 2 of 6)
mem_245_oe_n
Output
H
Low
mem_245_dt_r_n output_clk PCI Interface pci_ad[31:0]
Output
Z
High High
Output cpu_mas terclk I/O Z
PCI
pci_cbe_n[3:0]
I/O
Z
PCI
pci_par
I/O
Z
PCI
pci_frame_n
I/O
Z
PCI
pci_trdy_n pci_irdy_n pci_stop_n pci_idsel_n pci_perr_n pci_serr_n
I/O I/O I/O Input I/O I/O Opencollector Input Input
Z Z Z
PCI PCI PCI --
Z Z
PCI PCI
pci_clk pci_rst_n
-- L --
pci_devsel_n
I/O
Z
PCI
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Drive Reset Strength State Status Capability
Name
Type
Description
pci_req_n[2]
Input
Z
--
PCI Bus Request #2 Negated Requires an external pull-up. Host mode: pci_req_n[2] is an input indicating a request from an external device. Satellite mode: used as pci_idsel pin which selects this device during a configuration read or write. Alternate function: pci_idsel (satellite). PCI Bus Request #0 Negated Requires an external pull-up for burst mode. Host mode: pci_req_n[0] is an input indicating a request from an external device. Satellite mode: pci_req_n[0] is an output indicating a request from this device. PCI Bus Grant #2 Negated Recommend an external pull-up. Host mode: pci_gnt_n[2] is an output indicating a grant to an external device. Satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin. External pull-up is required. Alternate function: pci_inta_n (satellite). PCI Bus Grant #1 Negated Recommend external pull-up. Host mode: not used as pci_gnt_n[1]. Must be used as alternate function PIO[7]. Satellite mode: Not used as pci_gnt_n[1]. Used as pci_eprom_cs output pin for Serial Chip Select for loading PCI Configuration Registers in the RC32332 Reset Initialization Vector PCI boot mode. Defaults to the output direction at reset time. 1st Alternate function: pci_eeprom_cs (satellite). 2nd Alternate function: PIO[7]. PCI Bus Grant #0 Negated Host mode: pci_gnt_n[0] is an output indicating a grant to an external device. Recommend external pullup. Satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. Requires external pull-up. PCI Interrupt #A Negated Uses pci_gnt_n[2]. See the PCI subsection.
pci_req_n[0]
I/O
Z
High
pci_gnt_n[2]
Output
Z1
High
pci_gnt_n[1] (can only be used as alternate function)
I/O
X for 1 pci clock then H2
High
pci_gnt_n[0]
I/O
Z
High
pci_inta_n
Output Opencollector Input
Z
PCI
pci_lock_n
--
PCI Lock Negated Driven by the Bus Master to indicate that an exclusive operation is occurring.
1 Z in host mode; L in satellite non-boot mode; Z in satellite boot mode.
2 H in host mode, L in satellite non-boot and boot modes. X = unknown.
SDRAM Control Interface sdram_addr_12 Output L High SDRAM Address Bit 12 and Precharge All SDRAM mode: Provides SDRAM address bit 12 (10 on the SDRAM chip) during row address and "precharge all" signal during refresh, read and write command. SDRAM RAS Negated SDRAM mode: Provides SDRAM RAS control signal to all SDRAM banks. SDRAM CAS Negated SDRAM mode: Provides SDRAM CAS control signal to all SDRAM banks. SDRAM WE Negated SDRAM mode: Provides SDRAM WE control signal to all SDRAM banks. SDRAM Clock Enable SDRAM mode: Provides clock enable to all SDRAM banks. SDRAM Chip Select Negated Bus Recommend an external pull-up. SDRAM mode: Provides chip select to each SDRAM bank. SODIMM mode: Provides upper select byte enables [7:4]. Table 1 Pin Descriptions (Part 3 of 6)
sdram_ras_n sdram_cas_n sdram_we_n sdram_cke sdram_cs_n[3:0]
Output Output Output Output Output
H H H H H
High High High High High
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Drive Reset Strength State Status Capability
Name
Type
Description
sdram_s_n[1:0]
Output
H
High
SDRAM SODIMM Select Negated Bus SDRAM mode: Not used. SDRAM SODIMM mode: Upper and lower chip selects. SDRAM Byte Enable Mask Negated Bus (DQM) SDRAM mode: Provides byte enables for each byte lane of all DRAM banks. SODIMM mode: Provides lower select byte enables [3:0]. SDRAM FCT245 Output Enable Negated Recommend an external pull-up. SDRAM mode: Controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. SDRAM FCT245 Direction Transmit/Receive Recommend an external pull-up. Uses cpu_dt_r_n. See CPU Core Specific Signals below. DMA Ready Negated Bus Requires an external pull-up. Ready mode: Input pin for general purpose DMA channel 0 that can initiate the next datum in the current DMA descriptor frame. Done mode: Input pin for general purpose DMA channel 0 that can terminate the current DMA descriptor frame. dma_ready_n[0] 1st Alternate function PIO[0]; 2nd Alternate function: dma_done_n[0]. Programmable Input/Output General purpose pins that can each can be configured as a general purpose input or general purpose output. These pins are multiplexed with other pin functions: pci_gnt_n[1] (pci_eeprom_cs), spi_mosi, spi_sck, spi_ss_n, spi_miso, uart_rx[0], uart_tx[0], dma_ready_n[0]. Note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time. The others default to inputs. UART Receive Data Bus UART mode: UART channel receive data. uart_rx[0] Alternate function: PIO[2]. UART Transmit Data Bus Recommend an external pull-up. UART mode: UART channel send data. Note that this pin defaults to an input at reset time and must be programmed via the PIO interface before being used as a UART output. uart_tx[0] Alternate function: PIO[1]. SPI Data Output Serial mode: Output pin from RC32332 as an Input to a Serial Chip for the Serial data input stream. In PCI satellite mode, acts as an Output pin from RC32332 that connects as an Input to a Serial Chip for the Serial data input stream for loading PCI Configuration Registers in the RC32332 Reset Initialization Vector PCI boot mode. 1st Alternate function: PIO[6]. Defaults to the output direction at reset time. 2nd Alternate function: pci_eeprom_mdo. SPI Data Input Serial mode: Input pin to RC32332 from the Output of a Serial Chip for the Serial data output stream. In PCI satellite mode, acts as an Input pin from RC32332 that connects as an output to a Serial Chip for the Serial data output stream for loading PCI Configuration Registers in the RC32332 Reset Initialization Vector PCI boot mode. Defaults to input direction at reset time. 1st Alternate function: PIO[3]. 2nd Alternate function: pci_eeprom_mdi. Table 1 Pin Descriptions (Part 4 of 6)
sdram_bemask_n [3:0] sdram_245_oe_n
Output
H
High
Output
H
Low
sdram_245_dt_r_n On-Chip Peripherals dma_ready_n[0]
Output
Z
High
I/O
Z
Low
pio[7:0]
I/O
See related pins
Low
uart_rx[0]
I/O
Z
Low
uart_tx[0]
I/O
Z
Low
spi_mosi
I/O
L
Low
spi_miso
I/O
Z
Low
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Drive Reset Strength State Status Capability
Name
Type
Description
spi_sck
I/O
L
Low
SPI Clock Serial mode: Output pin for Serial Clock. In PCI satellite mode, acts as an Output pin for Serial Clock for loading PCI Configuration Registers in the RC323332 Reset Initialization Vector PCI boot mode. 1st Alternate function: PIO[5]. Defaults to the output direction at reset time. 2nd Alternate function: pci_eeprom_sk. SPI Chip Select Output pin selecting the serial protocol device as opposed to the PCI satellite mode EEPROM device. Alternate function: PIO[4]. Defaults to the output direction at reset time. CPU Non-Maskable Interrupt Requires an external pull-up. This interrupt input is active low to the CPU. CPU Master System Clock Provides the basic system clock. CPU Interrupt Requires an external pull-up. These interrupt inputs are active low to the CPU. CPU Cold Reset This active-low signal is asserted to the RC32332 after Vcc becomes valid on the initial power-up. The Reset initialization vectors for the RC32332 are latched by cold reset. CPU Direction Transmit/Receive This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during read operations. 1st Alternate function: mem_245_dt_r_n. 2nd Alternate function: sdram_245_dt_r_n. JTAG Test Clock Requires an external pull-down. An input test clock used to shift into or out of the Boundary-Scan register cells. jtag_tck is independent of the system and the processor clock with nominal 50% duty cycle. JTAG Test Data In Requires an external pull-up. On the rising edge of jtag_tck, serial input data are shifted into either the Instruction or Data register, depending on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the debug unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG). This pin is also used as the ejtag_dint_n signal in the EJTAG mode. JTAG Test Data Out The jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. When no data is shifted out, the jtag_tdo is tri-stated. During Real Time Mode, this signal provides a nonsequential program counter at the processor clock or at a division of processor clock. This pin is also used as the ejtag_tpc signal in the EJTAG mode. JTAG Test Mode Select Requires an external pull-up. The logic signal received at the jtag_tms input is decoded by the TAP controller to control test operation. jtag_tms is sampled on the rising edge of the jtag_tck. JTAG Test Reset When neither JTAG nor EJTAG are being used, jtag_trst_n must be driven low (pulled down) or the jtag_tms/ejtag_tms signals must be pulled up and jtag_clk actively clocked. EJTAG Test Clock Processor Clock. During Real Time Mode, this signal is used to capture address and data from the ejtag_tpc signal at the processor clock speed or any division of the internal pipeline. Table 1 Pin Descriptions (Part 5 of 6)
spi_ss_n
I/O
H
Low
CPU Core Specific Signals cpu_nmi_n cpu_masterclk cpu_int_n[1:0] cpu_coldreset_n Input Input Input Input L -- -- -- --
cpu_dt_r_n
Output
Z
--
JTAG Interface Signals jtag_tck Input --
jtag_tdi, ejtag_dint_n
Input
--
jtag_tdo, ejtag_tpc
Output
Z
High
jtag_tms
Input
--
jtag_trst_n
Input
L
--
ejtag_dclk
Output
Z
--
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Drive Reset Strength State Status Capability
Name
Type
Description
ejtag_pcst[2:0]
I/O
Z
Low
EJTAG PC Trace Status Information 111 (STL) Pipe line Stall 110 (JMP) Branch/Jump forms with PC output 101 (BRT) Branch/Jump forms with no PC output 100 (EXP) Exception generated with an exception vector code output 011 (SEQ) Sequential performance 010 (TST) Trace is outputted at pipeline stall time 001 (TSQ) Trace trigger output at performance time 000 (DBM) Run Debug Mode Alternate function: modebit[2:0]. EJTAG DebugBoot Requires an external pull-down. The ejtag_debugboot input is used during reset and forces the CPU core to take a debug exception at the end of the reset sequence instead of a reset exception. This enables the CPU to boot from the ICE probe without having the external memory working. This input signal is level sensitive and is not latched internally. This signal will also set the JtagBrk bit in the JTAG_Control_Register[12]. EJTAG Test Mode Select Requires an external pull-up. The ejtag_tms is sampled on the rising edge of jtag_tck. Debug CPU versus DMA Negated De-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from the CPU. Assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from DMA. Alternate function: modebit[6]. Debug CPU Acknowledge Negated Indicates either a data acknowledge to the CPU or DMA. Alternate function: modebit[4]. Debug CPU Address/Data Strobe Negated Assertion indicates that either a CPU or a DMA transaction is beginning and that the mem_data[31:4] bus has the current block address. Alternate function: modebit[5]. Debug CPU Instruction versus Data Negated Assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a CPU or DMA data transaction. De-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a CPU instruction transaction. Alternate function: modebit[3]. Table 1 Pin Descriptions (Part 6 of 6)
ejtag_debugboot
Input
--
ejtag_tms Debug Signals debug_cpu_dma_n
Input
--
I/O
Z
Low
debug_cpu_ack_n
I/O
Z
Low
debug_cpu_ads_n
I/O
Z
Low
debug_cpu_i_d_n
I/O
Z
Low
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IDT 79RC32332--Rev. Y
Logic Diagram -- RC32332
CPU Core signals
mem_addr[22:2]
cpu_masterclk cpu_coldreset_n cpu_nmi_n cpu_int_n[1:0] cpu_dt_r_n
mem_data[31:0]
mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] mem_wait_n mem_245_oe_n mem_245_dt_r_n output_clk
pci_req_n[2] pci_gnt_n[0] pci_gnt_n[2] pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_mdo pci_eeprom_cs pci_eeprom_sk
RC32332
Logic Symbol
sdram_ras_n sdram_cas_n sdram_we_n sdram_cke sdram_cs_n[3:0] sdram_bemask_n[3:0] sdram_245_oe_n sdram_245_dt_r_n sdram_s_n_[1:0]
dma_ready_n[0] jtag_tck jtag_tms jtag_tdi jtag_tdo jtag_trst_n uart_rx[0] uart_tx[0] ejtag_dclk ejtag_pcst[2:0] ejtag_tms ejtag_debugboot ejtag_tpc pio[7:0]
JTAG Interface
debug_cpu_dma_n debug_cpu_ack_n debug_cpu_i_d_n debug_cpu_ads_n Gnd Vss
Debug
Power/ Ground
Vcc to I/O Vcc to core VccP VssP
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PIO Interface
Vcc I/O Vcc core
EJTAG
UART
DMA Interface
SDRAM Signals
pci_cbe_n[3:0] pci_ad[31:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[0]
spi_mosi
spi_ss_n spi_sck sdram_addr[16:13] sdram_addr[12] sdram_addr[11:2]
PCI Interface
SPI Interface
spi_miso
Local System Interface
December 18, 2002
IDT 79RC32332--Rev. Y
Mode Bit Settings to Configure Controller on Reset
The following table lists the mode bit settings to configure the controller on reset.
Pin ejtag_pcst[2:0] Mode Bit 2:0 MSB (2) Description Clock Multiplier MasterClock is multiplied internally to generate PClock Value 0 1 2 3 4 5 6 7 debug_cpu_i_d_n debug_cpu_ack_n debug_cpu_ads_n debug_cpu_dma_n mem_addr[17] mem_addr[19:18] 3 4 5 6 7 9:8 MSB (9) EndBit Reserved Reserved TmrIntEn Enables/Disables the timer interrupt on Int*[5] Reserved for future use Boot-Prom Width specifies the memory port width of the memory space which contains the boot prom. 0 1 0 0 0 1 1 00 01 10 11 Table 2 Boot-Mode Configuration Settings 8 bits 16 bits 32 bits Reserved Enables timer interrupt Disables timer interrupt Mode Setting Multiply by 2 Multiply by 3 Multiply by 4 Reserved Reserved Reserved Reserved Reserved Little-endian ordering Big-endian ordering
reset_boot_mode Settings By using the non-boot mode reset initialization mode the user can change the internal register addresses from base 1800_0000 to base 1900_0000, as required. The RC32332 reset-boot mode initialization setting values and mode descriptions are listed below.
Pin Reset Boot Mode Description Tri-state memory bus and EEPROM bus during coldreset_n assertion Reserved PCI-boot mode (pci_host_mode must be in satellite mode) RC32332 will reset either from a cold reset or from a PCI reset. Boot code is provided via PCI. Standard-boot mode Boot from the RC32332's memory controller (typical system). Table 3 RC32332 reset_boot_mode Initialization Settings Value Mode Settings 11 10 01 00 PCI_boot_mode standard_boot_mode Tri-state_bus_mode
mem_addr[22:21] 1:0 MSB (1)
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pci_host_mode Settings During reset initialization, the RC32332's PCI interface can be set to the Satellite or Host mode settings. When set to the Host mode, the CPU must configure the RC32332's PCI configuration registers, including the read-only registers. If the RC32332's PCI is in the PCI-boot mode Satellite mode, read-only configuration registers are loaded by the serial EEPROM.
Pin mem_addr[20] Reset Boot Mode PCI host mode Description PCI is in satellite mode PCI is in host mode (typical system) Table 4 RC32332 pci_host_mode Initialization Settings Value 1 0 Mode Settings PCI_satellite PCI_host
Clock Parameters -- RC32332
(Ta = 0C to +70C Commercial, Ta = -40C to +85C Industrial, Vcc I/O = +3.3V5%,Vcc Core = +3.3V5%)
Parameter cpu_masterclock HIGH cpu_masterclock LOW cpu_masterclock period1 cpu_masterclock Rise & Fall Time2 cpu_masterclock Jitter pci_clk Rise & Fall Time pci_clk Period1 jtag_tck Rise & Fall Time ejtag_dck period jtag_tck clock period ejtag_dclk High, Low Time ejtag_dclk Rise, Fall Time output_clk3 cpu_coldreset_n Asserted during power-up cpu_coldreset_n Rise Time
1. 2. 3.
Symbol tMCHIGH tMCLOW
tMCP
Test Conditions Transition 2ns Transition 2ns -- -- PCI 2.2 --
RC32332 100MHz Min 8 8 20 -- -- -- 20 -- 10 100 4 -- N/A Max -- -- 66.6 3 + 250 1.6 -- 5 -- -- -- 1 N/A -- 5
RC32332 133MHz Min 6.75 6.75 15 -- -- -- 20 -- 10 100 4 -- N/A 120 -- Max -- -- 66.6 3 + 250 1.6 -- 5 -- -- -- 1 N/A -- 5
RC32332 150MHz Min 6 6 13.33 -- -- -- 20 -- 10 100 4 -- N/A 120 -- Max -- -- 66.6 3 + 200 1.6 -- 5 -- -- -- 1 N/A -- 5
Units ns ns ns ns ps ns ns ns ns ns ns ns -- ms ns
tMCRise, tMCFall -- tJITTER tPCRise, tPCFall tPCP tJCRise, tJCFall tDCK, t11 tTCK, t3 tDCK High, t9 tDCK Low, t10 tDCK Rise, t9 tDCK Fall, t10 tDO21 power-on sequence tCRRise
120 --
Table 5 Clock Parameters - RC32332
cpu_masterclock should never be below pci_clk if PCI interface is used. Rise and Fall times are measured between 10% and 90%.
Output_clk should not be used in a system. Only the cpu_masterclock or its derivative must be used to drive all the subsystems with designs based on the RC32334/RC32332. Refer to the RC32334/RC32332 Device Errata for more information.
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Reset Specification
VCC cpu_masterclk (MClk) cpu_coldreset_n
tCRRise
modebit[9:0] >= 110 ms 120 ms Figure 3 Mode Configuration Interface Reset Sequence >= 10 ms
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AC Timing Characteristics -- RC32332 (Ta = 0C to +70C Commercial, Ta = -40C to +85C Industrial, Vcc I/O = +3.3V5%,Vcc Core = +3.3V5%)
RC323321 100MHz Min Max RC323321 133MHz Min Max RC323321 150MHz Min Max User Manual Timing Diagram Reference
Signal
Symbol
Reference Edge
Units
Local System Interface mem_data[31:0] (data phase) mem_data[31:0] (data phase) cpu_dt_r_n mem_data[31:0] mem_data[31:0] output hold time mem_data[31:0] (tristate disable time) mem_data[31:0] (tristate to data time) mem_wait_n mem_wait_n mem_addr[22:2] mem_cs_n[5:0] mem_oe_n, mem_245_oe_n mem_we_n[3:0] mem_245_dt_r_n mem_addr[25:2] mem_cs_n[5:0] mem_oe_n, mem_we_n[3:0], mem_245_dt_r_n, mem_245_oe_n PCI pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_lock_n3 pci_idsel, pci_req_n[2], pci_req_n[0], pci_gnt_n[0], pci_inta_n pci_gnt_n[0] pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_lock_n3 Tsu pci_clk rising 3 -- 3 -- 3 -- ns Tsu2 Thld2 Tdo3 Tdo4 Tdoh1 Tdz Tzd Tsu6 Thld8 Tdo5 Tdo6 Tdo7 Tdo7a Tdo8 Tdoh3 cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 6 1.5 -- -- 1 -- -- 9 1 -- -- -- -- -- 1.5 -- -- 15 12 -- 122 122 -- -- 12 12 12 15 15 -- 5 1.5 -- -- 1 -- -- 7 1 -- -- -- -- -- 1.5 -- -- 12 10 -- 102 102 -- -- 9 9 9 12 12 -- 4.8 1.5 -- -- 1 -- -- 6 1 -- -- -- -- -- 1.5 -- -- 10 9.3 -- 9.32 9.32 -- -- 8 8 8 10 10 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Chapter 10, Figures 10.6 through 10.8 Chapter 9, Figures 9.2 and 9.3
Tsu
pci_clk rising
5
--
5
--
5
--
ns
Tsu Thld
pci_clk rising pci_clk rising
5 0
-- --
5 0
-- --
5 0
-- --
ns ns Per PCI 2.2
Table 6 AC Timing Characteristics - RC32332 (Part 1 of 4)
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IDT 79RC32332--Rev. Y RC323321 100MHz Min Max RC323321 133MHz Min Max RC323321 150MHz Min Max User Manual Timing Diagram Reference
Signal
Symbol
Reference Edge
Units
pci_idsel, pci_req_n[2], pci_req_n[0], pci_gnt_n[0], pci_inta_n pci_eeprom_mdi pci_eeprom_mdi pci_eeprom_mdo, pci-eeprom_cs pci_eeprom_sk pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n pci_req_n[0], pci_gnt_[2], pci_gnt_n[1], pci_gnt_n[0], pci_inta_n SDRAM Controller sdram_245_dt_r_n sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_s_n[1:0], sdram_bemask_n[3:0], sdram_cke sdram_addr_12 sdram_245_oe_n sdram_245_dt_r_n sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_s_n[1:0], sdram_bemask_n[3:0] sdram_cke, sdram_addr_12, sdram_245_oe_n DMA dma_ready_n[0], dma_done_n[0] dma_ready_n[0], dma_done_n[0] Interrupt Handling cpu_int_n[1:0], cpu_nmi_n cpu_int_n[1:0], cpu_nmi_n
Thld
pci_clk rising
0
--
0
--
0
--
ns
Tsu Thld Tdo Tdo Tdo
pci_clk rising, pci_eeprom_sk falling pci_clk rising, pci_eeprom_sk falling pci_clk rising, pci_eeprom_sk falling pci_clk rising pci_clk rising
15 15 -- -- 2
-- -- 15 15 7.5
12 12 -- -- 2
-- -- 12 12 7.5
10 10 -- -- 2
-- -- 10 10 7.5
ns ns ns ns ns Per PCI 2.2
Tdo
pci_clk rising
2
7.5
2
7.5
2
7.5
ns
Tdo8 Tdo9
cpu_masterclk rising cpu_masterclk rising
-- --
15 12
-- --
12 9
-- --
10 8
ns ns
Chapter 11, Figures 11.4 and 11.5
Tdo10 Tdo11 Tdoh4 Tdoh4
cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising
-- -- 1 2.5
12 12 -- --
-- -- 1 2.5
9 9 -- --
-- -- 1 2.5
8 8 -- --
ns ns ns ns
Tsu7 Thld9
cpu_masterclk rising cpu_masterclk rising
9 1
-- --
7 1
-- --
6 1
-- --
ns ns Chapter 13, Figure 13.4 Chapter 14, Figure 14.12
Tsu9 Thld13
cpu_masterclk rising cpu_masterclk rising
9 1
-- --
7 1
-- --
6 1
-- --
ns ns
Table 6 AC Timing Characteristics - RC32332 (Part 2 of 4)
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IDT 79RC32332--Rev. Y RC323321 100MHz Min Max RC323321 133MHz Min Max RC323321 150MHz Min Max User Manual Timing Diagram Reference
Signal
Symbol
Reference Edge
Units
PIO PIO[7:0] PIO[7:0] PIO[7:6], PIO[4:0] PIO[5] PIO[7:6], PIO[4:0] PIO[5] UARTs uart_rx[0], uart_tx[0] uart_rx[0], uart_tx[0] uart_rx[0], uart_tx[0] uart_rx[0], uart_tx[0] Reset mem_addr[19:17] mem_addr[19:17] mem_addr[22:20] mem_addr[22:20] Debug Interface debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n, ejtag_pcst[2:0] debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n, ejtag_pcst[2:0] debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n Tsu20 cpu_coldreset_n rising 10 -- 10 -- 10 -- ms Tsu10 Thld10 Tsu22 Thld22 cpu_coldreset_n rising cpu_coldreset_n rising cpu_masterclk rising cpu_masterclk rising 10 1 9 1 -- -- -- -- 10 1 7 1 -- -- -- -- 10 1 6 1 -- -- -- -- ms ns ns ns Chapter 19, Figures 19.8 and 19.9 Tsu7 Thld9 Tdo16 Tdoh8 cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 15 15 -- 1 -- -- 15 -- 12 12 -- 1 -- -- 12 -- 10 10 -- 1 -- -- 10 -- ns ns ns ns Chapter 17, Figure 17.16 Tsu7 Thld9 Tdo16 Tdo19 Tdoh7 Tdoh7 cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising cpu_masterclk rising 9 1 -- -- 1 1 -- -- 15 15 -- -- 7 1 -- -- 1 1 -- -- 12 12 -- -- 6 1 -- -- 1 1 -- -- 10 10 -- -- ns ns ns ns ns ns Chapter 15, Figures 15.9 and 15.10
Thld20
cpu_coldreset_n rising
1
--
1
--
1
--
ns
Chapter 19, Figure 19.9 and Chapter 9, Figure 9.2
Tdo20
cpu_masterclk rising
--
15
--
12
--
10
ns
Tdoh20
cpu_masterclk rising
1
--
1
--
1
--
ns
Table 6 AC Timing Characteristics - RC32332 (Part 3 of 4)
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IDT 79RC32332--Rev. Y RC323321 100MHz Min Max RC323321 133MHz Min Max RC323321 150MHz Min Max User Manual Timing Diagram Reference
Signal
Symbol
Reference Edge
Units
JTAG Interface jtag_tms, jtag_tdi, jtag_trst_n jtag_tms, jtag_tdi, jtag_trst_n jtag_tdo EJTAG Interface ejtag_tms, ejtag_debugboot ejtag_tms, ejtag_debugboot jtag_tdo Output Delay Time jtag_tdi Input Setup Time jtag_tdi Input Hold Time jtag_trst_n Low Time jtag_trst_n Removal Time ejtag_tpc Output Delay Time ejtag_pcst Output Delay Time
1. At all pipeline frequencies. 2.
t5 t6 t4 t5 t6 tTDODO, t4 tTDIS, t5 tTDIH, t6 tTRSTLow, t12 tTRSTR, t13 tTPCDO, t8 tPCSTDO, t7
jtag_tck rising jtag_tck rising jtag_tck falling jtag_tclk rising jtag_clk rising jtag_tck falling jtag_tck rising jtag_tck rising -- jtag_tck rising ejtag_dclk rising ejtag_dclk rising
10 10 -- 4 2 -- 4 2 100 3 -1 -1
-- -- 10 -- -- 6 -- -- -- -- 3 3
10 10 -- 4 2 -- 4 2 100 3 -1 -1
-- -- 10 -- -- 6 -- -- -- -- 3 3
10 10 -- 4 2 -- 4 2 100 3 -1 -1
-- -- 10 -- -- 6 -- -- -- -- 3 3
ns ns ns ns ns ns ns ns ns ns ns ns See Figure 4 below. See Figure 4 below.
Table 6 AC Timing Characteristics - RC32332 (Part 4 of 4)
Guaranteed by design.
3. pci_rst_n is tested per PCI 2.2 as an asynchronous signal.
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IDT 79RC32332--Rev. Y
Standard EJTAG Timing
--
RC32332
Figure 4 represents the timing diagram for the EJTAG interface signals. The standard JTAG connector is a 10-pin connector providing 5 signals and 5 ground pins. For Standard EJTAG, a 24-pin connector has been chosen providing 12 signals and 12 ground pins. This guarantees elimination of noise problems by incorporating signal-ground type arrangement. Refer to the RC32334/RC32332 User Reference Manual for connector pinout and mechanical specifications.
t3 jtag_tck t14 ejtag_dclk t1 t14 t2 t15 jtag_tdi/ejtag_dint_n ejtag_tms, jtag_tms t5 jtag_tdo t4 ejtag_pcst[2:0] t7 jtag_trst_n t6 jtag_tdo t8
ejtag_tpc,ejtag_pcst[2:0] capture
t11 t15 t9 t10
jtag_tdo/ejtag_tpc, ejtag_tpc[8:2]
ejtag_tpc
ejtag_pcst
t13 Notes to diagram: t1 = tTCKlow t2 = tTCKHIGH t3 = tTCK t4 = tTDODO t5 = tTDIS t6 = tTDIH t7 = tPCSTDO t8 = tTPCDO t9 = tDCKHIGH t10 = tDCKLOW Figure 4 Standard EJTAG Timing t11 = t12 = t13 = t14 = t15 = tDCK tTRSTDO tTRSTR tTCK RISE, tTCK FALL tDCK RISE, tDCK FALL
t12
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IDT 79RC32332--Rev. Y
Output Loading for AC Testing
VREF
+1.5V
- + CLD
To Device Under Test
Signal All High Drive Signals All Low Drive Signals 50 pF 25 pF
Cld
Figure 5 Output Loading for AC Testing
Note: PCI pins have been correlated to PCI 2.2.
Recommended Operation Temperature and Supply Voltage
Grade Commercial Industrial Ambient Temperature 0C to +70C Ambient -40C to +85C Ambient Gnd 0V 0V VccIO 3.3V5% 3.3V5% VccCore 3.3V5% 3.3V5% VccP 3.3V5% 3.3V5%
Table 7 Temperature and Voltage
DC Electrical Characteristics -- RC32332
Commercial Temperature Range--RC32332 (Ta = 0C to +70C Commercial, Ta = -40C to +85C Industrial, Vcc I/O = +3.3V5%,Vcc Core = +3.3V5%)
RC323321 Minimum -- Maximum 0.4V -- 0.8V -- 0.4V -- 0.8V -- Table 8 DC Electrical Characteristics - RC32332 (Part 1 of 2) 1- 5, 8, 13-15, 18-25, 28-35, 38-40, 49-51, 53- 57, 60, 61, 63, 6567,70-76, 79, 80, 83-87, 90-94, 153, 154, 156, 158, 165, 194, 201, 204, 205, 206 |IOUT| = 7mA |IOUT| = 16mA --
Parameter LOW Drive OutputPads VOL VOH VIL VIH HIGH Drive OutputPads VOL VOH VIL VIH
Pin Numbers 41-45, 48, 170, 171, 174, 175, 177-180, 185-190, 195-200, 207, 208
Conditions |IOUT| = 6mA |IOUT| = 8mA --
Vcc - 0.4V
-- 2.0V --
Vcc - 0.4V
-- 2.0V
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IDT 79RC32332--Rev. Y Parameter PCI Drive OutputPads VOL VOH VIL VIH CIN CIN CIN COUT I/OLEAK I/OLEAK
1. At all pipeline frequencies.
RC323321 Minimum -- -- -- -- -- 5pf Maximum -- -- -- -- 10pF 12pF 8pF -- -- -- 10pF 10A 50A 152, 168 155 156 All output pads
Pin Numbers 96, 97, 100-109, 112-119, 122, 124-129, 132-139, 142-149, 152
Conditions Per PCI 2.2
-- Per PCI 2.2 Per PCI 2.2 -- Input/Output Leakage Input/Output Leakage
All non-internal pull-up pins All internal pull-up pins
Table 8 DC Electrical Characteristics - RC32332 (Part 2 of 2)
Capacitive Load Deration -- RC32332 Refer to the IDT document 79RC32332 IBIS Model located on the company's web site.
Power Consumption -- RC32332
Note: This table is based on a 2:1 pipeline-to-bus clock ratio.
Parameter 100MHz RC32332 Typical ICC P (mA) Normal mode (mA) Standby mode1 Power dissipation (W) Normal mode Power dissipation (W) Standby mode1 360 250 1.2 .87 Max. 480 370 1.7 1.3 133MHz RC32332 Typical 480 330 1.5 1.1 Max. 630 480 2.2 1.7 150MHz RC32332 Typical 550 390 1.7 1.3 Max. 700 540 2.4 1.9 CL = (See Figure 5, Output Loading for AC Testing) Ta = 25oC Vcc core = 3.46V (for max. values) Vcc I/O = 3.46V (for max. values) Vcc core = 3.3V (for typical values) Vcc I/O = 3.3V (for typical values)
Conditions
Table 9 Power Consumption
1. RISCore 32300 CPU core enters Standby mode by executing WAIT instructions. On-chip logic outside the CPU core continues to function.
Power Ramp-up There is no special requirement for how fast Vcc and VccP ramp up to 3.3V. However, all timing references are based on Vcc and VccP stabilized at 3.3V -5%.
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Power Curves
The following two graphs contain the simulated power curves that show power consumption at various bus frequencies. Note: Only pipeline frequencies that are integer multiples (2x, 3x, 4x) of bus frequencies are supported.
550.0 500.0 450.0 400.0 350.0 300.0 250.0 200.0 150.0 100.0
ICC (mA @3.46V I/O & Core)
2x 3x 4x
15 20 25 30 35 40 45 50 55 60 65 70 75 System Bus Speed (MHz)
Figure 6 Typical Power Usage - RC32332
.
750.0 650.0 550.0 3x 450.0 4x 350.0 250.0 150.0 15 20 25 30 35 40 45 50 55 60 65 70 75 System Bus Speed (MHz)
Figure 7 Maximum Power Usage - RC32332
ICC (mA @ 3.46V I/O & core)
2x
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Absolute Maximum Ratings
Symbol VCC Vi Vimin Ta, Industrial Tstg
1. Functional
Parameter Supply Voltage Input Voltage Input Voltage - undershoot Ambient Operating Temperature Storage Temperature
2
Min1 -0.3 -0.3 -0.6 -40 -40
Max1 3.465 5.5 -- 85 125 V V V
Unit
degrees C degrees C
Table 10 Absolute Maximum Ratings
and tested operating conditions are given in Table 7. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. All PCI pads are fully compatible with PCI Specification version 2.2.
Package Pin-out -- 208-PQFP for RC32332
The following table lists the pin numbers and signal names for the RC32332. Signal names ending with an _n are active when low.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function sdram_245_oe_n sdram_we_n sdram_cas_n sdram_bemask_n[0] sdram_bemask_n[1] Vss Vcc I/O sdram_cs_n[0] sdram_cs_n[1] sdram_ras_n sdram_s_n[0] sdram_s_n[1] mem_addr[2] mem_addr[3] mem_addr[4] Vss Vcc I/O mem_addr[5] mem_addr[6] mem_addr[7] mem_addr[8] 1 1 1 1 1 1 1 Alt Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Function mem_data[12] mem_data[19] mem_data[13] mem_data[18] mem_data[14] Vss Vcc I/O mem_data[17] mem_data[16] Vcc core mem_data[15] cpu_masterclk mem_data[31] mem_data[0] mem_data[30] Vss Vcc I/O mem_data[1] mem_data[29] mem_data[2] mem_data[28] Alt Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 Function pci_ad[7] pci_cbe_n[0] pci_ad[8] pci_ad[9] pci_ad[10] Vss Vcc I/O pci_ad[11] pci_ad[12] pci_ad[13] pci_ad[14] pci_ad[15] pci_cbe_n[1] pci_par pci_serr_n Vss Vcc I/O pci_perr_n pci_lock_n pci_stop_n pci_devsel_n Alt Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 Function pci_req_n[2] pci_gnt_n[2] pci_rst_n cpu_int_n[0] cpu_int_n[1] Vss Vcc I/O jtag_tdi jtag_tdo jtag_tms ejtag_tms jtag_tck jtag_trst_n ejtag_pcst[0] ejtag_pcst[1] 1 1 Alt 1 1
Vss
Vcc I/O ejtag_pcst[2] ejtag_dclk ejtag_debugboot debug_cpu_i_d_n 1 1
Table 11 RC32332 208-pin QFP Package Pin-Out (Part 1 of 2)
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IDT 79RC32332--Rev. Y Pin 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Function mem_addr[9] mem_addr[10] mem_addr[11] output_clk Alt 1 1 1 Pin 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 1 1 1 1 1 1 1 91 92 93 94 95 96 97 98 99 1 100 101 102 103 104 Function mem_data[3] mem_data[27] mem_data[4] Vccp Vssp mem_data[26] mem_data[5] Vss Vcc core cpu_dt_r_n mem_data[25] mem_data[6] mem_data[24] mem_data[7] Vss Vcc I/O mem_data[23] mem_data[8] mem_data[22] mem_data[9] mem_data[21] cpu_nmi_n pci_ad[0] pci_ad[1] Vss Vcc I/O pci_ad[2] pci_ad[3] pci_ad[4] pci_ad[5] pci_ad[6] 2 Alt Pin 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Function pci_trdy_n pci_irdy_n pci_frame_n pci_cbe_n[2] Vss Vcc core pci_ad[16] pci_ad[17] pci_ad[18] pci_ad[19] pci_ad[20] pci_ad[21] pci_ad[22] pci_ad[23] Vss Vcc I/O pci_cbe_n[3] pci_ad[24] pci_ad[25] pci_ad[26] pci_ad[27] pci_ad[28] pci_ad[29] pci_ad[30] Vss Vcc I/O pci_ad[31] pci_req_n[0] pci_gnt_n[0] pci_clk pci_gnt_n[1] 2 Alt Pin 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function debug_cpu_ads_n debug_cpu_ack_n debug_cpu_dma_n Vcc Core Alt 1 1 1
Vss
Vcc core mem_addr_12 sdram_addr_12 sdram_cke sdram_cs_n[2] sdram_cs_n[3] sdram_bemask_n[2] sdram_bemask_n[3] mem_addr[13] Vss Vcc I/O mem_addr[14] mem_addr[15] mem_addr[16] mem_addr[17] mem_addr[18] mem_addr[19] mem_addr[20] mem_addr[21] Vss Vcc I/O mem_addr[22] mem_data[10] mem_data[11] mem_data[20] cpu_coldreset_n
Vss Vcc core Vcc Core
spi_ss_n spi_sck spi_miso spi_mosi dma_ready_n[0] mem_245_oe_n mem_wait_n Vss Vcc I/O mem_oe_n mem_cs_n[0] mem_cs_n[1] mem_cs_n[2] mem_cs_n[3] mem_cs_n[4] mem_cs_n[5] mem_we_n[0] Vss Vcc I/O mem_we_n[1] mem_we_n[2] mem_we_n[3] uart_tx[0] uart_rx[0] 1 1 2 1 2 2 2 2
Table 11 RC32332 208-pin QFP Package Pin-Out (Part 2 of 2)
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IDT 79RC32332--Rev. Y
RC32332 Alternate Signal Functions
Pin 13 14 15 18 19 20 21 22 23 24 35 38 39 Alt #1 sdram_addr[2] sdram_addr[3] sdram_addr[4] sdram_addr[5] sdram_addr[6] sdram_addr[7] sdram_addr[8] sdram_addr[9] sdram_addr[10] sdram_addr[11] sdram_addr[13] sdram_addr[14] sdram_addr[15] Alt #2 Pin 40 41 42 43 44 45 48 83 156 157 158 170 171 Alt #1 sdram_addr[16] modebit[7] modebit[8] modebit[9] reset_pci_host_mode reset_boot_mode[0] reset_boot_mode[1] mem_245_dt_r_n sdram_245_dt_r_n Alt #2 Pin 174 177 178 179 180 185 186 187 188 189 191 207 208 Alt #1 modebit[2] modebit[3] modebit[5] modebit[4] modebit[6] PIO[4] PIO[5] PIO[3] PIO[6] PIO[0] sdram_wait_n PIO[1] PIO[2] pci_eeprom_sk pci_eeprom_mdi pci_eeprom_mdo dma_done_n[0] mem_wait_n Alt #2
pci_eeprom_cs (satellite) PIO[7] pci_idsel (satellite) pci_inta_n (satellite) modebit[0] modebit[1]
Table 12 RC32332 Alternate Signal Functions
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IDT 79RC32332--Rev. Y
RC32332 Package Drawing -- 208-pin PQFP
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IDT 79RC32332--Rev. Y
RC32332 Package Drawing
-- Page Two
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IDT 79RC32332--Rev. Y
Ordering Information
79RCXX Product Type
V Operating Voltage
DDD Device Type
SSS CPU Frequency
PP Package Temp range/ Process
Blank = Commercial Temperature (0 C to +70 C Ambient) I = Industrial Temperature (-40 C to +85 C Ambient) 100MHz 133MHz 150MHz DH = 208-pin PQFP
332
V = 3.3V 5% 79RC32 = 32-bit family product
Valid Combinations
79RC32V332 - 100DH, 133DH, 150DH 79RC32V332 - 100DHI, 133DHI, 150DHI Commercial Industrial
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com
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for Tech Support: email: rischelp@idt.com phone: 408-492-8208
December 18, 2002

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